Remarkable advances in machine learning and artificial intelligence have been made in various domains, achieving near-human performance in a plethora of cognitive tasks including vision, speech and natural language processing. However, implementations of such cognitive algorithms in conventional “von-Neumann” architectures are orders of magnitude more area and power expensive than the biological brain. Therefore, it is imperative to search for fundamentally new approaches so that the improvement in computing performance and efficiency can keep up with the exponential growth of the AI computational demand.
Crossbar in-memory (CiM) computing architecture is a promising solution for providing efficient computational intelligence. Crossbar memory arrays provide in-situ matrix-vector multiplication (MVM) processing with massive parallelism. These multiple CiM cores need to be interconnected through peripheral circuitry such as analog-to-digital converters (ADC) to provide noise-resilient data communication in the digital domain. However, the ADC circuitry is found to be the bottleneck in mixed-signal CiM hardware and dominate the energy consumption, chip area and latency. We are interested in explorations of multiple ways to mitigate such ADC bottleneck. Exemplary approaches include reconfigurable A-D conversion, hardware-aware sparsification and pruning of DNN models, precision reduction of intermediate MVM output, circuit-architecture-algorithm co-optimization.
